A selectable-bandwidth 3.5 mW, 0.03 mm(2) self-oscillating Sigma Delta modulator with 71 dB dynamic range at 5 MHz and 65 dB at 10 MHz bandwidth

In this paper we present a dual-mode third order continuous time Sigma Delta modulator that combines noise shaping and pulse-width-modulation (PWM). In our 0.18 micro-m CMOS prototype chip the clock frequency equals 1 GHz, but the PWM carrier is only around 125 MHz. By adjusting the loop filter, the ADC bandwidth can be set to 5 or 10 MHz. In the 5 MHz mode the peak SNDR equals 64 dB and the dynamic range 71 dB. In the 10 MHz mode the peak SNDR equals 58 dB and the DR 65 dB. This performance is achieved at an attractively low silicon area of 0.03 mm^2 and a power consumption of 3.5 mW

A dual-mass capacitive-readout accelerometer operated near pull-in

A mechanical two-mass configuration and a readout circuit for a single-axis capacitive-readout accelerometer with ΣΔ force-feedback is presented. The system reduces electrical and quantisation input-referred noise through the use of negative springs, reduced gaps in the readout capacitors and maximised readout voltage. A theoretical analysis and simulation results are discussed

A very compact 1MS/s Nyquist-rate A/D-converter with 12 effective bits

We present a very compact analog-to-digital convertor (ADC) for use as a standard cell. To achieve an inherent accuracy of at least 12-bits without trimming or calibration, extended counting A/D-conversion is used. Here, the circuit performs a conversion by passing through two modes of operation: first it works as a 1st-order incremental convertor and then it is reconfigured to operate as a conventional algorithmic converter. This way, we obtain a Nyquist-rate converter that requires only 1 operational amplifier and achieves 12-bit accuracy performance in 13 clock cycles with 9 bit capacitor matching. The circuit is designed in 0.18 mu m CMOS with a thick oxide option. The resulting analog core occupies a chip area of only 0.011 mm2 and the complete digital control and reconstruction logic (including additional test features and storage registers) is 0.02 mm2. The analog blocks of the circuit consume 1.2mW and the digital 0.4mW. At a sample rate of 1 MS/s, the peak SNDR is 74.5dB and the dynamic range is 78dB, constant over the Nyquist band. The worst-case integral non-lineairity (INL) is within plus or minus 0.55 LSB

Robot competitions trick students into learning

It has been shown in the past that robots help to bring theoretical concepts into practice, while at the same time increasing the motivation of the students. Despite these benefits, robots are hardly ever integrated in education programs and at the same time students feel that they have the competences nor the infrastructure to build a robot on their own. Therefore the workgroup electronics (WELEK) of Ghent University gives students the opportunity to build a robot by organizing workshops and competitions. Up until now, four competitions were organized in which over 200 students voluntarily participated. This paper describes our approach in the hope that it will inspire other educators to do the same thing. We also measured the effectiveness of our competitions by sending each of the participants a questionnaire. The results confirm that students acquire relevant technical competences by building a robot, learn to work as a team and are challenged to use their creativity

Borrelia afzelii evidenced by polymerase chain reaction in a biopsy of nipple lymphocytoma.

https://spark.parkland.edu/theatre_images/3315/thumbnail.jp